The present invention relates generally to the routing phase of integrated circuit design, and more specifically, to congestion aware layer promotion.
Typically, integrated circuit (chip) design includes synthesis, placement, and routing stages that may be performed iteratively to develop the final design for fabrication of the integrated circuit. The design may be organized into equal-sized grids that each include a number of components such as transistors. The routing stage places interconnects between transistors within and among the various grids. These interconnects are placed in layers with the lowest (and generally slowest) layer being closest to the device and the highest (and generally fastest) layer being closest to the packaging of the chip.
One of the important design considerations is timing constraints. That is, the signals carried by the various interconnects must reach their intended destinations within specified timing requirements for the integrated circuit to function properly. The iterative process is undertaken in integrated circuit design in large part to ensure that the timing constraints are adhered to. During that process, one of the techniques that may be used to improve the timing of some interconnects is layer promotion. Layer promotion refers to moving or “promoting” an interconnect to a higher (and faster) level to improve timing.